In manufacturing a semiconductor device or an Integrated Circuit (IC) (more specifically during Back End processing), fine interconnect lines, typically made of metal such as copper, are used to provide connections to the device areas in the semiconductor device or IC and one or more interlayer dielectric (ILD) layers are used to provide isolation between the interconnect lines. The ILD material and interconnect lines act as a capacitor which slows down the propagation of signals through the interconnect lines. Thus, the dielectric constants k of the ILD layers, together with the resistance of the interconnect lines, affect the speed of signal propagation in an IC. In order to improve the speed of signal propagation, dielectric materials with low dielectric constants k are used for the ILD layers.
In the search for materials having the lowest dielectric constants and since air has the lowest relative dielectric constant of close to 1, techniques have been developed whereby air gaps or void space in the ILD layers are used to reduce interconnect capacitance and so improve the speed of signal propagation. The lowest dielectric constant can be achieved with air gaps of mesoscopic dimensions.
The formation of air gaps in ILD layers is well known. For example, U.S. Pat. No. 6,297,125 discloses a method of forming air gaps between two laterally spaced metal lines. U.S. Pat. No. 7,078,352 describes a method of forming air gaps in a semiconductor device. US patent application 2006/0258077 describes a method of forming via air gaps in a semiconductor substrate.
A problem with using air gaps in ILD layers is that the side surfaces and top surfaces of the interconnect lines are exposed to the ambient environment such that during subsequent process steps, contaminant material, such as etch gases or Chemical Mechanical Polishing (CMP) slurry, can seep through the porous ILD layers and enter the air gaps and attack the unprotected metal interconnect lines.
Some techniques for sealing the air gaps have been proposed. For example, U.S. Pat. No. 6,297,125 describes depositing a 50-100 nm layer of silicon dioxide over the metal lines to protect the metal, etching a sacrificial dielectric layer between the metal lines of the same interconnect level to the protection layer of silicon dioxide to form air gaps and then using thick (500-1000 nm) dielectric layers formed of Plasma-Enhanced TetraEthylOrthoSilicate (TEOS) oxide to enclose the top and bottom of the metal lines and the air gap structure. However, TEOS has a high dielectric constant and so such a sealing layer would negatively impact the speed of signal propagation in the IC. Furthermore, the etchants used to etch the sacrificial dielectric layer to form the air gaps is typically aggressive to all dielectric layers and therefore the protection layer of silicon dioxide has to be thick (50-100 nm) and has a high dielectric constant k.
US patent application no. 2006/0258077 also describes using a TEOS oxide layer to seal the air gaps.
U.S. Pat. No. 7,078,352 discloses forming air gaps and forming a thick passivation layer over the metal lines.
An article entitled ‘Dual Damascene Process for Air-Gap Cu Interconnects Using Conventional CVD Films as Sacrificial Layers’ by Shouichi Uno, Junji Noguchi, Hiroshi Ashihara, Takayuki Oshima, Kiyohiko Sato, Nobuhiro Konishi, Tatsuyuki Saito and Kazusato Hara, Interconnect Technology Conference, 2005, Proceedings of the IEEE 2005 International, 6-8 Jun. 2005, pages 174-176 describes forming an air gap between metal lines of the same interconnect level and then forming a barrier SiCN film on the metal lines in the air gap.
However, none of the known techniques provide adequate and reliable sealing of the air gaps and ILD layers to avoid corrosion or contamination or erosion of the interconnect lines whilst not impacting negatively the speed of signal propagation in the IC.